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Advanced Analog Technology, Inc.
May 2008
AAT1415/AAT1415A
Product information presented is for internal use within AAT Inc. only. Details are subject to change without notice.
FIVE-CHANNEL DC-DC CONVERTER WITH A 2.5V LDO
FEATURES
Complete PWM Power Control Circuitry Input Voltage Range: 1.5 to 5.5V Low Start-Up Voltage: 1.2V Independent On / Off Control for All Channels Internal Soft-Start for All Channels Power-OK Outputs & Overload Protection Adjustable Operation Frequency with External Components Ranging from 100kHz to 1MHz VQFN-40 5*5 Package Available
GENERAL DESCRIPTION
The AAT1415/AAT1415A provides an integrated 5-channel pulse-width-modulation (PWM) solution and a low noise LDO for the power supply of DC-DC converter. This device improves performance and size compared to conventional controllers in battery design. The AAT1415/AAT1415A has three current mode PWM converters (CH1, CH2, and CH3) and two voltage mode PWM converters (CH4 and CH5). Each current-mode channel has on-chip synchronous power FETs. The five channels include: CH1: Boost /buck selectable DC-DC converter, which activates PWM function at 1.2V when it is configured as a boost converter. CH2: Boost / buck selectable DC-DC converter. CH3: Buck DC-DC converter. CH4: Boost DC-DC controller for the CCD positive bias. CH5: Inverting DC-DC controller for the CCD negative bias.
APPLICATIONS
Digital Still Cameras Digital Videos PDAs Portable Devices
PIN CONFIGURATION
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AAT1415/AAT1415A
ORDERING INFORMATION
DEVICE TYPE AAT1415 PART NUMBER AAT1415 -Q8-T AAT1415A -Q8-T PACKAGE Q8: VQFN 40-5*5 Q8: VQFN 40-5*5 PACKING T: Tape and Reel T: Tape and Reel TEMP. RANGE MARKING AAT1415 XXXXX XXXX AAT1415A XXXXX XXXX
-40 C to +85 C
MARKING DESCRIPTION 1. Part Name 2. Lot No. (6~9 Digits) 3. Date Code (4 Digits) 1. Part Name 2. Lot No. (6~9 Digits) 3. Date Code (4 Digits)
AAT1415A
-40 C to +85 C
NOTE: All AAT products are lead free and halogen free.
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage (VDD) Pin Voltage 1 (OUT1, OUT2, VDDC, C3RDY, C4RDY, VDD5, SEL1, SEL2, TR1) Pin Voltage 2 (OUT3, VREF, OSC, EO_, EN_, IN_) Pin Voltage 3 (OUT5) Pin Voltage 4 (OUT4) Pin Voltage 5 (V2P5) Pin Voltage 6 (GND_) Input Voltage 7 (SW1) Input Voltage 8 (SW2) Input Voltage 9 (SW3) SW1 Current SW2 Current SW3 Current Open Drain NMOS Current (C3RDY, C4RDY) Operating Temperature Range Storage Temperature Range SYMBOL VALUE -0.3 to + 6.0 -0.3 to + 6.0 -0.3 to (VDD + 0.3) -0.3 to (VDD5 + 0.3) -0.3 to (VDD + 0.3) -0.3 to (VDDC + 0.3) 0.3 to + 0.3 -0.3 to (OUT1 + 0.3V) -0.3 to (OUT2 + 0.3V) -0.3 to (OUT3 + 0.3V) 3.6 3.6 3.6 10 -40 C to + 85 C -65 C to + 150 C UNIT V V V V V V V V V V A A A mA
VMDD VI1 VI2 VI3 VI4 VI5 VI6 VI7 VI8 VI9 ISW1 ISW 2 ISW3 IOD TC
TSTORAGE
C C
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RECOMMENDED OPERATING CONDITIONS
PARAMETER Operating Free-Air Temperature SYMBOL MIN -40 MAX +85 UNIT
TC
C
ELECTRICAL CHARACTERISTICS
( TC = 25 C , VDD = OUT1 = OUT2 = OUT3 = 3.6V, unless otherwise specified.)
General Item
PARAMETER Input Voltage Range VDD Under-Voltage Lockout VDD Under-Voltage Lockout Hysteresis CH1 Minimum Startup Voltage Shutdown Supply Current Into VDD Supply Current Into VDD with CH1 Enable Supply Current Into VDD with CH2 Enable Supply Current Into VDD with CH3 Enable Supply Current Into VDD with CH1 And CH4 Enable Supply Current Into VDD with CH1 And CH5 Enable Supply Current Into VDD with CH1 And LDO Enable SYMBOL TEST CONDITION MIN 2.6 2.35 2.40 80 1.2 0.10 EN1 = 3.6V, IN1 = 1.5V EN2 = 3.6V, IN2 = 1.5V EN3 = 3.6V, IN3 = 1.5V EN1 = EN4 = 3.6V, IN1 = IN4 = 1.5V EN1 = EN5 = 3.6V, IN1 = 1.5V, IN5 = -0.5V EN1 = 3.6V, IN1 = 1.5V 450 400 400 550 550 100 1.5 10.0 700 650 650 800 800 300 TYP MAX 5.5 2.45 UNIT V V mV V
VVDD VUVLO VUHYS VSTART ISHDN ICH1 ICH2 ICH3 ICH4 ICH5 ICHC
A A A A A A A
Reference Voltage
PARAMETER Reference Output Voltage Reference Load Regulation Reference Line Regulation SYMBOL TEST CONDITION MIN 1.23 TYP 1.25 4.50 1.3 MAX 1.27 10.0 5.0 UNIT V %/mV %/mA
VREF
IREF = 20 A
10 A < IREF <200 A 2.7V< VDD <5.5V
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ELECTRICAL CHARACTERISTICS
( TC = 25 C , VDD = OUT1 = OUT2 = OUT3 = 3.6V, unless otherwise specified.)
Oscillator
PARAMETER OSC Discharge Trip Level OSC Discharge Resistance OSC Discharge Pulse Width OSC Frequency SYMBOL TEST CONDITION Rising Edge OSC = 1.5V, IOSC = 30mA MIN 1.225 TYP 1.250 52 150 MAX 1.275 80 UNIT V
VODT RODR t OFF
fOSC
ns kHz
ROSC = 47k , COSC = 100pF
500
Power Fail Latch and Thermal Protection
PARAMETER CH4, CH5 Overload Condition CH1, CH2 Overload Threshold SYMBOL TEST CONDITION Duty Cycle MIN TYP 100 1.07 1.07 0.600 1.10 1.10 0.625 100,000 1.13 1.13 0.650 MAX UNIT % V V V Cycles
VF12 VF13
CH3 Overload Threshold Overload Protection Fault Delay Thermal Shutdown Thermal Hysteresis
IN1, IN2, Fail Detection Voltage IN3 Fail Detection Voltage (AAT1415) IN3 Fail Detection Voltage (AAT1415A)
TSHDN THYS
160 20
C C
Logic Inputs
PARAMETER EN_, SEL_ Input Low Level EN_, SEL_ Input High Level SEL_ Input Leakage EN_ Impedance to GND TR1 Output Low Voltage SYMBOL TEST CONDITION MIN TYP MAX 0.4 1.4 0.1 200 1.2mA Into TR1 300 0.1 1.0 400 0.2 UNIT V V
VIL VIH IL9 REN VTRL
A
k
V
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ELECTRICAL CHARACTERISTICS
( TC = 25 C , VDD = OUT1 = OUT2 = OUT3 = 3.6V, unless otherwise specified.)
CH1 (Boost / Buck)
PARAMETER IN1 Regulation Voltage IN1 to EO1 Transconductance CH1 Maximum Duty Cycle IN1 Input Leakage Current Current-Sense Amplifier Transresistance OUT1 Leakage Current SW1 Leakage Current Switch On-Resistance SYMBOL TEST CONDITION IN1 = EO1 IN1 = EO1 Boost Mode (SEL1 = VDD ) Buck Mode (SEL1 = GND) 85 MIN 1.231 TYP 1.250 70 90 100 -100 0.01 0.25 0.5 0.1 0.1 95 m P Channel Boost Mode (SEL1 = VDD ) Buck Mode (SEL1 = GND) 200 3 0.8 4,096 A A OSC Cycles 2.65 V mV ns kHz 5.0 5.0 +100 95 MAX 1.269 UNIT V
VIN1
S
% % nA V/A V/A
IL1
IN1 = 0V to 1.5V Boost Mode (SEL1 = VDD ) Buck Mode (SEL1 = GND)
ILO1 ILSW1
SEL1 = GND VSW1 = 0V, OUT1 = 3.6V SEL1 = GND VSW1 = OUT1 = 3.6V N Channel
A A
RON1(N) RON1(P) ILIMIT1(N)
SW1 Peak Current Limit Soft-Start Interval OUT1 Startup-to-Normal Operating Threshold OUT1 Startup-to-Normal Operating Hysteresis Startup t OFF Startup Frequency
ILIMIT1(P)
VUVLO1 VUHYS1
tOS fSTART
Rising Edge
2.30
2.50 80
VDD = 1.8V VDD = 1.8V
700 200
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ELECTRICAL CHARACTERISTICS
( TC = 25 C , VDD = OUT2 = 3.6V, unless otherwise specified.)
CH2 (Boost / Buck)
PARAMETER IN2 Regulation Voltage IN2 to EO2 Transconductance CH2 Maximum Duty Cycle IN2 Input Leakage Current Current-Sense Amplifier Transresistance OUT2 Leakage Current SW2 Leakage Current Switch On-Resistance SYMBOL TEST CONDITION IN2 = EO2 IN2 = EO2 Boost Mode (SEL2 = VDD ) Buck Mode (SEL2 = GND) 85 MIN 1.231 TYP 1.250 70 90 100 -100 0.01 0.25 0.5 0.1 0.1 95 m P Channel Boost Mode (SEL2 = VDD ) Buck Mode (SEL2 = GND) 150 3 0.8 4,096 A A OSC Cycles 2.55 V mV 5.0 5.0 +100 95 MAX 1.269 UNIT V
VIN2
S
% % nA V/A V/A
IL2
IN2 = 0V to 1.5V Boost Mode (SEL2 = VDD ) Buck Mode (SEL2 = GND)
ILO2 ILSW 2 RON2(N) RON2(P) ILIMIT2(N)
VSW 2 = 0V, OUT2 = 3.6V VSW 2 = OUT2 = 3.6V
N Channel
A A
SW2 Peak Current Limit Soft-Start Interval OUT2 Under-Voltage Lockout in Buck Mode OUT2 Under-Voltage Lockout in Hysteresis
ILIMIT2(P)
VUVLO2 VUHYS2
SEL2 = GND
2.45
2.50 80
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AAT1415/AAT1415A
ELECTRICAL CHARACTERISTICS
( TC = 25 C , VDD = OUT3 = 3.6V, unless otherwise specified.)
CH3 (Buck)
PARAMETER IN3 Regulation Voltage IN3 to EO3 Transconductance CH3 Maximum Duty Cycle IN3 Input Leakage Current Current-Sense Amplifier Transresistance SW3 Leakage Current Switch On-Resistance SW3 Current Limit Soft-Start Interval SW3 Peak Current Limit Soft-Start Interval C3RDY Output Low Voltage C3RDY Leakage Current SYMBOL TEST CONDITION IN3 = EO3 (AAT1415) IN3 = EO3 (AAT1415A) IN3 = EO3 MIN 1.231 0.784 TYP 1.250 0.800 70 100 MAX 1.269 V 0.816 UNIT
VIN3
S
% +100 nA V/A 5.0
IL3
IN3 = 0V to 1.5V
-100
0.01 0.5
ILSW3 RON3(N) RON3(P) ILIMIT3
VSW3 = 0V to 3.6V
N Channel P Channel
0.1 95
A
m
150 0.8 4,096 A OSC Cycles A OSC Cycles 0.10 1.00 V
ILIMIT3(N)
0.8 2,048
VC3RDY IC3RDY
0.1mA Into C3RDY EN3 = GND
0.01 0.01
A
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AAT1415/AAT1415A
ELECTRICAL CHARACTERISTICS
( TC = 25 C , VDD = OUT3 = 3.6V, unless otherwise specified.)
CH4 (Buck)
PARAMETER IN4 Regulation Voltage IN4 to EO4 Transconductance CH4 Maximum Duty Cycle IN4 Input Leakage Current OUT4 Driver Resistance Soft-Start Interval C4RDY Output Low Voltage C4RDY Leakage Current SYMBOL TEST CONDITION IN4 = EO4 IN4 = EO4 IN4 = 0V 85 -100 MIN 1.231 TYP 1.250 70 90 0.01 5 5 4,096 95 +100 MAX 1.269 UNIT V
VIN4
S
% nA
IL4 RON4(N) RON4(P)
IN4 = 0V to 1.5V
IOUT4 = 10mA IOUT4 = -10mA

OSC Cycles 0.10 1.00 V
VC4RDY IC4RDY
0.1mA Into C4RDY EN4 = GND
0.01 0.01
A
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ELECTRICAL CHARACTERISTICS
( TC = 25 C , VDD = OUT1 = 3.6V, unless otherwise specified.)
CH5
PARAMETER IN5 Regulation Voltage IN5 to EO5 Transconductance Maximum Duty Cycle IN5 Input Leakage Current OUT5 Driver Resistance Soft-Start Interval VDD5 Under-Voltage Lockout Threshold VDD5 Under-Voltage Lockout Hysteresis IN5 = 0V 85 -100 SYMBOL TEST CONDITION MIN -0.01 TYP 0.00 70 90 0.1 5 5 4,096 95 +100 MAX +0.01 UNIT V
VIN5
S
% nA
IL5 RON5(N) RON5(P)
IN5 = 0V to 0.5V
IOUT5 = 10mA IOUT5 = -10mA

OSC Cycles 2.65 V mV
VUVLO5 VUHYS5
Rising Edge
2.30
2.50 80
ELECTRICAL CHARACTERISTICS
( TC = 25 C , VDD = VDDC = 3.6V, unless otherwise specified.)
2.5V LDO
PARAMETER Input Voltage Range V2P5 Regulation Voltage V2P5 Dropout Voltage V2P5 LDO Output Current V2P5 LDO Output Current Limit V2P5 VDDC PSRR V2P5 Line Regulation V2P5 Load Regulation Measure VV2P5 SYMBOL TEST CONDITION MIN 2.6 2.45 2.50 TYP MAX 5.5 2.55 50 100 150 60 UNIT V V mV mA mA dB 10 5 %/mV %/mA
VVDDC VV2P5 VDROP25 VV2P5 ILIMC25
IV2P5 = 10mA IV2P5 = 10mA IV2P5 = 10mA
VVDDC = 2.6V ~ 5V
Measure VV2P5 IV 2P 5 = 5mA ~ 100mA
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TYPICAL OPERATING CHARACTERISTICS
VIN=1.8V , VOUT = 4.4V , IOUT = 250mA
VIN = 3 V ,VOUT = 4.4V
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TYPICAL OPERATING CHARACTERISTICS
VIN =4.2V ,VOUT=3.3V , I OUT= 300mA
VIN =4V , V OUT=3.3V
0
VIN =1.8V ,VOUT=3.3V , IOUT=300mA
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TYPICAL OPERATING CHARACTERISTICS
VIN=2.5V,VOUT=3.3V
VIN =4V ,VOUT=2.5V , I OUT= 250mA
VIN = 3V , VOUT = 2.5V
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TYPICAL OPERATING CHARACTERISTICS
VIN =3V , VOUT=1.5V , IOUT=250mA
VIN =3V , VOUT=1.5V
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TYPICAL OPERATING CHARACTERISTICS
VIN =3V , VOUT=12V
VIN =3V , VOUT=12V , IOUT=30mA
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TYPICAL OPERATING CHARACTERISTICS
VIN =3V , VOUT=-8V , IOUT=50mA
VIN =3V , VOUT=-8V
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PIN DESCRIPTION
PIN NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 NAME EN3 IN3 EO3 OUT3 SW3 GND3 GND1 SW1 OUT1 SEL1 EO1 IN1 EN1 VREF OSC C4RDY C3RDY TR1 SEL2 EN2 IN2 EO2 OUT2 SW2 GND2 V2P5 VDDC I/O I I I/O I I/O I/O I/O I I/O I I O I/O O O I/O I I I I/O I I/O O I ON/OFF Control for CH3 CH3 Feedback Input CH3 Compensation Node CH3 Switching Power Input CH3 Switching Node CH3 Power Ground CH1 Power Ground CH1 Switching Node Switching Power Input (Boost) / Output (Buck) of CH1 Configures CH1 as a Buck or a Boost Converter CH1 Compensation Node CH1 Feedback Input ON/OFF Control for CH1 Reference Output Oscillator Control Power-Ok Signal for CH4 Power-Ok Signal for CH3 CH1 Feedback Resistor Truly Shutdown Input Configures CH2 as a Buck or a Boost Converter ON/OFF Control for CH2 CH2 Feedback Input CH2 Compensation Node CH2 Switching Power Input CH2 Switching Node CH2 Power Ground 2.5V LDO Output LDO Power Input FUNCTION
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28 29 30 31 32 33 34 35 36 37 38 39 40 GNDC EN5 IN5 EO5 VDD5 OUT5 GND IN4 EO4 EN4 OUT4 GND4 VDD I I I/O I O I I/O I I/O I LDO Ground ON/OFF Control for CH5 CH5 Feedback Input CH5 Compensation Node CH5 Power Source CH5 Gate-Drive Output Internal Circuit Ground CH4 Feedback Input CH4 Compensation Node ON/OFF Control for CH4 CH4 Gate-Drive Output CH4 Power Ground Internal Circuit Power Source
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FUNCTION BLOCK DIAGRAM
40
VDD
13 12 11
EN1 Fault Protection IN1 Vref EO1 Soft-Start Sawtooth1 Current Sense Current Limit SW1 PreDriver Digital Block OSC Current Sense Current Limit Digital Block Vref Soft-Start VF13 Fault Protection VF13
EN2
20 21 22
IN2 EO2
Current Limit OUT1
Sawtooth1 OUT2
9 8 7 10 18
23 24 25 19 1 2 3
PreDriver
SW2
GND1 SEL1 Step-up / Step-down Step-up / Step-down
GND2 SEL2
TR1
EN1 Fault Protection VF13
EN3
37 35 36
EN4
IN3 EO3 Vref Soft-Start
IN4
Fault Protection
EO4 Soft-Start Vref Current Sense Current Limit Digital Block OSC OSC GND3 Low Voltage OSCillator VDD OUT1 EN5 UVLO Digital Block Sawtooth1 OUT3
Sawtooth2 OUT4
4 5 6 29 30 31
38 39 GND4
PreDriver
SW3
15
OSC
Normal OSCillator
Fault Protection
IN5 EO5 0V Soft-Start
14
VREF
Reference
Sawtooth2
2.5V OSC
Digital Block 2.5V LDO
VDD5
32 33
OUT5 C4RDY VF13
28 26
GNDC V2P5 IN4
16
27
VDDC GND
VF13 IN3
17
C3RDY
34
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TYPICAL APPLICATION CIRCUIT
Figure 1. Typical 2-Cell AA-Powered System
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TYPICAL APPLICATION CIRCUIT
Figure 2. Typical 1-Cell Li+ Powered System (For CCD)
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TYPICAL APPLICATION CIRCUIT
Figure 3. Typical 1-Cell Li+ Powered System (For CMOS)
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C3RDY
complete
May 2008
AAT1415/AAT1415A
DETAILED DESCRIPTION
The AAT1415/AAT1415A is a power-conversion IC for digital still cameras. It can accept input from a variety of sources, including single-cell Li+ batteries and 2-cell alkaline or NiMH batteries. The AAT1415/AAT1415A includes five DC-DC converter channels and a 2.5V LDO to generate all required voltages: Synchronous-rectified converter with boost or buck DC-DC on-chip MOSFETs--Typically
C3RDY pulls low when IN3 reaches VF13 (1.1V typ). C3RDY goes high impedance in shutdown, overload, and thermal limit when IN3 is under VF13. A typical use for C3RDY is to enable 3.3V power to the CPU I/O after the CPU core is powered up (Figure 1), thus providing safe sequencing in hardware without system intervention.
C4RDY
C4RDY pulls low when IN4 reaches VF13 (1.1V typ). C4RDY goes high impedance in shutdown, overload, and thermal limit when IN4 is under VF13. A typical use for C4RDY is to drive a PMOS that gates 5V power to the CCD until the VH CCD bias (generated by CH4) is powered up (Figure 4).
supplies 4.6V for lens motor or 3.3V for main system power. Synchronous-rectified boost or Buck DC-DC converter with on-chip MOSFETs-- Typically supplies 3.3V for main system power or 2.5V for DDR. Synchronous-rectified buck DC-DC converter with on-chip MOSFETs-- Typically supplies 1.5V for the DSP core. Boost controller-- Typically used for positive voltage to bias one or more of the LCD, CCD, and LED backlights. Inverter controller-- Typically supplies negative CCD bias when high current is needed for large pixel-count CCDs. 2.5V LDO-- Typically supplies 2.5V for analog-to-digital converter's reference voltage. The AAT1415/AAT1415A includes three versatile status outputs that can provide information to the system. All are open-drain outputs and can directly drive MOSFET switches to facilitate sequencing, disconnect loads during overloads, or perform other hardware-based functions.
Figure 4. C4RDY Application Circuit
Soft-Start
The AAT1415/AAT1415A channels feature a soft-start function that limits inrush current and prevent excessive battery loading at startup by ramping the output voltage of each channel up to the regulation voltage. This is accomplished by ramping the internal reference inputs to mostly channel error amplifier from 0V to the 1.25V reference voltage (CH5 from 1.25V to 0V) over a period of 4,096 oscillator cycles (16ms at 500kHz) when initial power is applied or when a channel is enabled. Soft-start of CH1 is different from others in order to avoid limiting startup capability with loading.
TR1
TR1 pulls low when EN1 pulls high. A typical use for TR1 is to reduce CH1 boost feedback network's leakage current when CH1 is disabled (Figure 1).
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Reference
May 2008
AAT1415/AAT1415A
See Figure 6. soft-start mechanism. CH3 soft-start ramp takes half the time (2,048 clock cycles) of the other channel ramps. This allows the CH3 and CH2 output (when set to 3.3V) to track each other and rise at nearly the same dV/dt rate on power-up. Once the step-down output reaches its regulation point (1.5V or 1.8V typ), the CH2 output (3.3V typ) continues to rise at the same ramp rate. See Figure 7 timing chart of soft-start. Connect a 0.1F ceramic bypass capacitor from VREF to GND. VREF is enabled when EN1, EN2 or EN3 is high. The AAT1415/AAT1415A has internal 1.250V references.
Oscillator
The AAT1415/AAT1415A operating frequency is set by an RC network (ROSC, COSC) at the OSC pin. The range of usable settings is 100kHz to 1MHz. The oscillation frequency changes as the forced voltage (VOSC) ramps upward following startup. The oscillation frequency is then constant once the main output is in regulation. At the beginning of a cycle, the timing capacitor charge through the resistor until it reaches VREF. The charge time, t1, is as follows:
2.5V LDO
The 2.5V LDO regulates the VDDC voltages when the reference voltage (VREF) is ready and VDDC voltage is greater than 2.5V.
Fault Protection
If any DC-DC converter channel remains faulted for 100,000 clock cycles (200ms at 500kHz), then all outputs latch off until the AAT1415/AAT1415A is reinitialized or by cycling the input power. The fault-detection circuitry for any channel is disabled during its initial turn-on soft-start sequence. An exception to the standard fault behavior is that there is no 100,000 clock-cycle delay in entering the fault state if the OUT1 pin is dragged below its 2.5V UVLO1 threshold or is shorted. The UVLO1 immediately triggers and shuts down all channels. The CH1 then continues to attempt to start. If the CH1 output short remains, these attempts do not succeed since OUT1 remains near ground. If a soft-short or overload remains on OUT1, the startup oscillator switches the internal NMOS, but fault is retriggered if regulation is not achieved by the end of the soft-start interval. If OUT1 is dragged below the input, the overload is supplied by the body diode of the internal synchronous rectifier or by a Schottky diode connected from the battery to OUT1.
t 1 - R OSC x C OSC x ln(1 -
1.25 ) VOSC
The capacitor voltage then decays to zero over time t 2 150ns . Choose COSC between 47pF and 330pF. Determine ROSC and VOSC. The oscillator frequency is as follows:
fOSC
1 t1 + t 2
Figure 5. Oscillator Circuit
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Soft-Start of CH1 Soft-Start of CH2
Soft-Start of CH3
Soft-Start of CH4
4,096 cycles 1.25V 64 Steps 0V IN4 EA EO4
Soft-Start of CH5
Figure 6. Soft-Start Mechanism
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Soft Start Waveform
Figure 8. Oscillator Frequency
Low-Voltage Startup Oscillator
The AAT1415/AAT1415A internal control and reference voltage circuitry receives power from VDD and do not function when VDD is less than 2.5V. To ensure low voltage startup, the CH1 employs a low-voltage startup oscillator (about 200kHz) that activates at 1.2V if a Schottky diode is connected from PWR to OUT1. The startup oscillator drives the internal NMOS at SW1 until VDD reaches 2.5V, at which point voltage control is passed to the normal oscillator (current-mode PWM circuitry). At low input voltages, the CH1 can have difficulty starting into heavy loads.
Figure 7. Timing Chart of Soft-Start
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Inductor Selection
May 2008
AAT1415/AAT1415A
DESIGN PROCEDURE
Programming the Output Voltage
The output voltage for each channel is programmed using a resistor divider from the output connected to the feedback pins. When setting the output voltage, connect a resistive voltage divider from the channel output to the corresponding IN_ input and then to GND. Choose the lower-side (IN_-to-GND) resistor, then calculate the upper-side (output-to-IN_) resistor as follows:
VOUT _ RUPPER _ = RLOWER _ - 1 (For Boost / buck), VIN_
- VOUT _ RUPPER _ = RLOWER _ (For Inverting), V REF
The inductor is typically selected to operate with continuous conduction mode (CCM) for best efficiency in boost or buck converter and discontinuous conduction mode (DCM) for better response ability in boost or inverting controller (Table 1 and Table 2). The recommended inductance value range is between 2.2H and 4.7H for boost. The recommended inductance value range is between 6.8H and 22H for buck. The recommended inductance value range is between 3.3H and 6.8H for Inverting. With the chosen inductance value, the peak current for the inductor in steady state operation can be calculated (Table 3). It also needs to be taken into account that load transients and error conditions may cause higher inductor currents. This also needs to be taken into account when selecting an appropriate inductor. Table 1. Response Ability for Various Topologies Topology Response Ability VIN Boost or L Inverting
Where VIN_ is the feedback regulation voltage, 1.250V (AAT1415/AAT1415A, VIN3 = 0.8V ), and typical values for RLOWER _ are in the range of 10 k to 100 k .
VIN - VOUT L VIN : Input Voltage, VOUT : Output Voltage,
Buck
L : Inductance, Response Ability Unit:
mA s
Table 2. DCM/CCM Critical Inductance Values Topology D DCM/CCM Figure 9a. Feedback Network (For Boost/Buck) Boost
1-
VIN VOUT
RLOAD D (1 - D)2 2 fSW (1 - D) RLOAD 2 fSW
RLOAD (1 - D)2 2 fSW
Buck
VOUT VIN
VOUT
Inverting
VOUT + VIN
VIN : Input Voltage, VOUT : Output Voltage,
Figure 9b. Feedback Network (For Inverting)
RLOAD : Loading, fSW : Switch Frequency,
Inductance Unit: Henry
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Table 3. Inductor Peak Current Topology Mode Peak Current Table 4. Diode and MOS Minimum Voltage Rating Topology Minimum Voltage Rating Boost Buck Inverting
CCM Boost
IO I + L, (1 - D) 2 VOUT D (1 - D) IL = , fSW L D = 1- VIN VOUT
VOUT VIN
VIN + VOUT
External MOSFET Selection
The boost controller and Inverting controller drive external logic-level MOSFETs. MOSFETs' maximum drain-to-source voltage ( VDS(MAX) ) rating must be greater than the value in Table 4. Their on-resistance ( RDS(ON) ), total gate charge ( QG ) and reverse transfer capacitance ( CRSS ) are the lower the better.
DCM
2 ( VOUT - VIN ) IO L f SW IL , 2 V (1 - D) , ( IL = OUT fSW L IO + V D= OUT ) VIN 2 (VIN - VOUT ) VOUT IO L fSW VIN V D I IO + L , ( IL = IN 2 fSW L
CCM Buck
Input Capacitor
The input current to converters are discontinuous, and therefore input capacitors are required to supply the AC current to converters while maintaining the DC input voltage. A low ESR capacitor is required to keep the noise at the IC to a minimum. Ceramic capacitors are preferred, but tantalum or low-ESR electrolytic capacitors may also suffice. For insuring stable operation a bypass ceramic 0.1F capacitor should be placed as close to the IC VDD pin as possible.
DCM
,
CCM Inverting
D=
VOUT VOUT + VIN
)
Output Capacitor
The output capacitor is required to maintain the DC output voltage. Low ESR capacitors are preferred to keep the output voltage ripple low. The characteristics of the output capacitor also affect the stability of the regulation control system. Ceramic, tantalum, or low ESR electrolytic capacitors are recommended. In the case of ceramic capacitors, the impedance at the switching frequency is dominated by the capacitance, and so the output voltage ripple is mostly independent of the ESR. The output voltage ripple is estimated to be:
DCM
2 VOUT IO L fSW
VIN : Input Voltage, VOUT : Output Voltage, IO : Output Current, L: Inductance, fSW : Switch Frequency, Peak Current Unit: Ampere
Schottky Diode Selection
Choose a Schottky diode who's maximum reverse voltage rating is greater than the value in Table 4, and who's current rating is greater than the peak inductor current.
VRIPPLE
IL 2 x fSW x COUT
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Where VRIPPLE is the output ripple voltage, IL is the following equation: inductor ripple current, fSW is the switching frequency and COUT is the output capacitance. In the case of tantalum or low- ESR electrolytic capacitors, the ESR dominates the impedance at the switching frequency, and so the output ripple is calculated as:
R C = IL(PK ) x
R CS TD% x VIN _ x Gm
VRIPPLE IL x RESR
Where VRIPPLE is the output voltage ripple, series resistance of the output capacitors. IL is the inductor ripple current, and RESR is the equivalent
Where IL(PK ) is the inductor peak current. The output filter capacitor (typically ceramic capacitor) is then chosen to cancel the RCCC zero:
COUT =
Boost Converter Compensation
The compensation resistor and capacitor (Figure 9a) are chosen to optimize control-loop stability. The boost converter employs current-mode control, thereby simplifying the control-loop compensation. When the converter operates with continuous conduction mode (typically the case), a right-half-plane zero appears in the loop-gain frequency response. To ensure stability, the cross over frequency ( fC ) should be much less than that of the right-half-plane zero. For CCM, the right-half-plane zero frequency ( fRHPZ ) is given by the following:
ILOAD x RCCC VOUT _
If the output filter capacitor (typically electrolytic capacitor) has significant equivalent series resistance (ESR), a zero occurs at the following:
ZESR =
1 2 x C OUT x RESR
If ZESR >> fC , it can be ignored. If ZESR is less than
fC , it should be cancelled with a pole set by capacitor CP connected from EO_ to GND: CP = C OUT x RESR RC
fRHPZ =
VOUT _ x (1 - D)2 2 x L x ILOAD
If the system wants better transient response, it can Typically target cross over frequency ( fC ) is the value for 1/6 of the RHPZ. Choose fC , and then calculate compensation capacitor ( CC ) as follows: parallel a capacitor CU with RUPPER _ from IN_ to
VOUT _ : CU = 1
CC =
VIN _ R CS
x
Gm (1 - D) x 2 fC ILOAD
V 2 x RUPPER _ x fC x IN _ VOUT _
If CP or CU is calculated to be less than 10pF, it can be omitted. Additionally, CP or CU can suppress the inrush current. So, for a 3.3V/250mA output with VI = 2.0V, L = 3.5H,
Where VIN _ is the feedback regulation voltage, 1.25V (typ), R CS is the current-sense amplifier transresistance, 0.25V/A (typ), GM is the error amplifier transconductance, 70S (typ). Select R C based on the allowed transient-droop ( TD% ) requirements by the
-
RUPPER = 164k, fSW = 500kHz and transient-droop
5%:
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CC = 1.25V 70 A / V (1 - 0.39) x x 3.3nF , 0.25V / A 2 35kHz 250mA
equation:
0.25V / A RC = 0.64 x 36k , 0.05 x 1.25 x 70 A / V 250mA COUT = x 36k x 3.3nF 10F 3.3V
When the COUT value is two to three times greater than what's calculated above, better output voltage ripple can be achieved.
R C = IL(PK ) x
R CS TD% x VIN _ x Gm
Where IL(PK ) is the inductor peak current. The output filter capacitor (typically ceramic capacitor) is then chosen to cancel the RCCC zero:
I COUT = LOAD x RCCC VOUT _
CU =
1 2 x 164k x 35kHz x (1.25V 3.3V )
100pF
If the output filter capacitor (typically electrolytic capacitor) has significant equivalent series resistance (ESR), a zero occurs at the following:
Buck Converter Compensation
The buck converter employs current-mode control, thereby simplifying the control-loop compensation. When the buck converter operates with continuous inductor current (typically the case), a RLOAD COUT pole appears in the loop-gain frequency response. To ensure stability, set the compensation RCCC (Figure 9a) to zero to compensate for the RLOAD COUT pole. Then set the loop crossover frequency below 1/5 of the switching frequency. The compensation resistor and
capacitor are then chosen to optimize control-loop stability.
ZESR =
1 2 x C OUT x RESR
If ZESR >> fC , it can be ignored. If ZESR is less than
fC , it should be cancelled with a pole set by capacitor CP connected from EO_ to GND: CP = C OUT x RESR RC
If the system wants better transient response, it can parallel a capacitor CU with RUPPER _ from IN_ to
Choose the compensation capacitor CC to set the desired crossover frequency fC . Determine the value by the following equation:
VOUT _ : CU = 1
Gm CC = x ILOAD x R CS 2 fC
where VIN _ is the feedback regulation voltage, 1.25V (typ), R CS is the current-sense amplifier transresistance, 0.5V/A (typ), Gm is the error amplifier transconductance, 70S (typ). Select RC based on the allowed transient-droop ( TD% ) requirements by the following
-
VIN _
V 2 x RUPPER _ x fC x IN _ VOUT _
If CP or CU is calculated to be less than 10pF, it can be omitted. So, for a 1.5V/250mA output with VI = 3.0V, L = 10H,
RUPPER = 20 k , fSW = 500kHz and transient-droop
3%:
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VOUT RLOAD COUT (2 VOUT - VI ) CC
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CC = 1.25V 70 A / V x 2.2nF , 250mA x 0.5V / A 2 70kHz 0.5V / A 68k , 0.03 x 1.25 x 70 A / V RC =
RC = 0.325A x
The typical RC is under 500 k . If the system wants better transient response, it can parallel a capacitor CU with RUPPER _ from IN_ to
250mA COUT = x 68k x 2.2nF 22F , 1.5V CU = 1 2 x 20k x 70kHz x (1.25V 1.5V ) 220pF .
VOUT _ : CU = 1
Boost Controller Compensation
The boost controller employs voltage-mode control to regulate their output voltage. A benefit of discontinuous conduction mode (DCM) is more flexible loop compensation, better response ability and no maximum duty-cycle restriction on boost ratio. When the boost converter operates with discontinuous conduction mode (typically the CCD VH case), the boost controller has a single pole at the following:
V 2 x RUPPER _ x fC x IN _ VOUT _
If CU is calculated to be less than 10pF, it can be omitted. Additionally, CU can suppress the inrush current So, for a 13V/30mA output with VI = 3.0V, L = 3.5 H ,
RUPPER = 100 k , fSW = 500kHz: CC = 13V 3V 70 A / V 13V x x (2 13V - 3V) 2 50kHz 8m (13V - 2V)
fP =
2 x VOUT - VI 2 x RLOAD x COUT x VOUT
4.7nF RC = 13V 433 10F 500k , (2 13V - 3V) 4.7nF 1 2 x 100k x 50kHz x 1.25V 330pF .
Set the loop cross over frequency ( fC ) below the lower of 1/10 the switching frequency ( fSW ). Choose the compensation capacitor CC to set the desired crossover frequency fC . Determine the value by the following equation:
CU =
(
13V )
Inverting Controller Compensation
VOUT VI VOUT Gm CC = x x (2 VOUT - VI ) 2 fC M ( VOUT - VI )
Where: The inverting controller also employs voltage-mode control to regulate their output voltage. To operate in discontinuous conduction mode (DCM) is preferred for simple loop compensation and freedom from duty-cycle restrictions on the inverter input-output ratio. When the Inverting converter operates with discontinuous
2 L fSW M= RLOAD
The RCCC zero is then used to cancel the fP pole, so:
conduction mode (typically the CCD VL case), the inverting controller has a single pole at the following: 1 fP = RLOAD COUT
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Set the loop cross over frequency ( fC ) below the lower of 1/10 the switching frequency ( fSW ). Choose the compensation capacitor CC to set the desired crossover frequency fC . Determine the value by the following equation:
CU =
1 VIN _ 2 x 56k x 20kHz x VOUT _ + VIN _
1nF
LAYOUT CONSIDERATIONS
Conductors carrying discontinuous currents and any high-current path should be made as short and wide as possible. The compensation network should be very close to the EO_ pin and avoid through VIA. The IC must be bypassed with ceramic capacitors placed close to the VDD and VREF. A separate low-noise ground plane containing the reference and signal grounds should connect to the power-ground plane at only one point to minimize the effects of power-ground currents. Typically, the ground planes are best joined right at the IC. Tie the feedback resistor divider to be very close to output capacitor and far away from the inductor or Schottky diode. Keep the feedback network (IN_) close to the IC. Switching nodes (SW_) should be kept as small as possible and should be routed away from high-impedance nodes such as IN.
Gm CC = x 2 fC ( VOUT + VREF ) M
Where:
VI
2 L fSW M= RLOAD
The RCCC zero is then used to cancel the fP pole, so:
RC =
RLOAD COUT 2 CC
The typical R C is under 500 k . If the system wants better transient response, it can parallel a capacitor CU with RUPPER _ from IN_ to
VOUT _ :
CU =
1 VIN _ 2 x RUPPER _ x fC x VOUT _ + VIN _
If CU is calculated to be less than 10pF, it can be omitted. Additional CU can suppress the inrush current. So, for a -7V/50mA output with VI = 3.0V, L = 4.7H,
RUPPER = 56 k , fSW = 500kHz: CC = 3V ( -7 + 1.25V) 33.6m 140 10F 300k , 2 2.2nF x 70 A / V 2.2nF 2 20kHz
RC =
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PACKAGE DIMENSION
VQFN40 5*5
Symbol A A1 b C D D2 E E2 e L y
Dimensions In Millimeters MIN TYP MAX 0.8 0.9 1.0 0.00 0.02 0.05 0.15 0.20 0.25 -----0.2 -----4.9 5.0 5.1 3.25 3.30 3.35 4.9 5.0 5.1 3.25 3.30 3.35 -----0.4 -----0.35 0.40 0.45 0 -----0.075
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